Magnetoresistive Random Access Memory (MRAM) is a non-volatile memory technology that has response (read/write) times comparable to volatile memory. In contrast to conventional RAM technologies which store data as electric charges or current flows, MRAM uses magnetic elements. As illustrated in FIGS. 1A and 1B, a magnetic tunnel junction (MTJ) storage element 100 can be formed from two magnetic layers 110 and 130, each of which can hold a magnetic field, separated by an insulating (tunnel barrier) layer 120. One of the two layers (e.g., fixed layer 110), is set to a particular polarity. The other layer's (e.g., free layer 130) polarity 132 is free to change to match that of an external field that can be applied. A change in the polarity 132 of the free layer 130 will change the resistance of the MTJ storage element 100. For example, when the polarities are aligned, FIG. 1A (parallel “P” magnetization low resistance state “0”), a low resistance state exists. When the polarities are not aligned, FIG. 1B (anti-parallel “AP” magnetization high resistance state “1”), then a high resistance state exists. The illustration of MTJ 100 has been simplified and those skilled in the art will appreciate that each layer illustrated may comprise one or more layers of materials, as is known in the art.
Referring to FIG. 2, a memory cell 200 of a conventional MRAM is illustrated for a read operation. The cell 200 includes a transistor 210, bit line 220, digit line 230 and word line 240. The cell 200 can be read by measuring the electrical resistance of the MTJ 100. For example, a particular MTJ 100 can be selected by activating an associated transistor 210 (transistor on), which can switch current from a bit line 220 through the MTJ 100. Due to the tunnel magnetoresistive effect, the electrical resistance of the MTJ 100 changes based on the orientation of the polarities in the two magnetic layers (e.g., 110, 130), as discussed above. The resistance inside any particular MTJ 100 can be determined from the current, resulting from the polarity of the free layer. Conventionally, if the fixed layer 110 and free layer 130 have the same polarity, the resistance is low and a “0” is read. If the fixed layer 110 and free layer 130 have opposite polarity, the resistance is higher and a “1” is read.
Unlike conventional MRAM, Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) uses electrons that become spin-polarized as the electrons pass through a thin film (spin filter). STT-MRAM is also known as Spin Transfer Torque RAM (STT-RAM), Spin Torque Transfer Magnetization Switching RAM (Spin-RAM), and Spin Momentum Transfer (SMT-RAM). During the write operation, the spin-polarized electrons exert a torque on the free layer, which can switch the polarity of the free layer. The read operation is similar to conventional MRAM in that a current is used to detect the resistance/logic state of the MTJ storage element, as discussed in the foregoing. As illustrated in FIG. 3A, a STT-MRAM bit cell 300 includes MTJ 305, transistor 310, bit line 320 and word line 330. The transistor 310 is switched on for both read and write operations to allow current to flow through the MTJ 305, so that the logic state can be read or written.
Referring to FIG. 3B, a more detailed diagram of a STT-MRAM cell 301 is illustrated, for further discussion of the react/write operations. In addition to the previously discussed elements such as MTJ 305, transistor 310, bit line 320 and word line 330, a source line 310, sense amplifier 350, read/write circuitry 360 and bit line reference 370 are illustrated. As discussed above, during a read operation, a read current is generated, which flows between the bit line 320 and source line 340 through MTJ 305. When the current is permitted to flow via transistor 310, the resistance (logic state) of the MTJ 305 can be sensed based on the voltage differential between the bit line 320 and source line 340, which is compared to a reference 370 and then amplified by sense amplifier 350. Those skilled in the art will appreciate the operation and construction of the memory cell 301 is known in the art. Additional details are provided, for example, in M. Hosomi, et al., A Novel Nonvolatile Memory with Spin Transfer Torque Magnetoresistive Magnetization Switching: Spin-RAM, proceedings of IEDM conference (2005), which is incorporated herein by reference in its entirety.
With reference now to FIG. 4, a circuit diagram for a conventional implementation of certain elements of FIG. 3B is illustrated. Specifically, FIG. 4 illustrates circuit implementations of reference 370 (reference current sensing) and sense amplifier 350 (voltage sensing) as employed during a read operation on STT-MRAM data cell 401 comprising MTJ 305 and transistor 310. As shown, a reference cell 402 comprises reference MTJ 404 and reference MTJ 406. The two reference MTJs 404 and 406 are programmed to “0” (P) and “1” (AP) states respectively before commencement of read/write operations. Load PMOS transistors 410 and 412 are coupled to the two reference MTJs 404 and 406 respectively, as shown in FIG. 4, such that a reference voltage “ref_in” is generated at node 408. One of ordinary skill will recognize that reference voltage ref_in corresponds to an average or mid-point voltage between voltages corresponding to the “0” and “1” states programmed in reference MTJs 404 and 406.
During a read operation, the data value stored in data cell 401 is evaluated as follows. The “read_en” signal is activated, such that current is flowed through data current sensing circuit 460. Activation of the word line, bit line, and source line corresponding to data cell 401 causes transistors 310, 416 and 418 to turn on and allow current to flow through MTJ 305. Load PMOS 424 enables a corresponding voltage, “data_in” to be generated at node 414. Comparison of voltage data_in with reference voltage ref_in, yields the state/value stored in data cell 401, wherein, if data_in is higher than ref_in, it can be determined that the value stored in data cell 401 is “1”; and if data_in is lower than ref_in, it can be determined that the value stored in data cell 401 is “0”.
The comparison of reference voltage ref_in and voltage data_in, and subsequent sensing of the value stored in data cell 401 is performed in sense amplifier 350. A pair of cross coupled inverters 420 and 422 magnify the voltage difference between data_in and ref_in to generate differential outputs “sao” and “saob” which correspond to the data value stored in data cell 401.
The above described conventional implementation for sensing the value stored in data cell 401 suffers from several limitations. Firstly, it is necessary to program reference cells, such as reference MTJs 404 and 406 to “0” and “1” values before read operations can be performed on data cells, such as data cell 401. This pre-programming or preparing of reference cells may give rise to several errors such as stuck-at faults, which may result in erroneous sensing of the value stored in the data cells. Secondly, design defects may cause shilling of the reference value ref_in to a value other than the ideal case value that is midway between “0” and “1”, such that a sensing margin for sensing the value stored in data cells, may be adversely affected. Thirdly, the utilization of two reference cells, one programmed to “0” and the other programmed to “1”, consumes valuable area on the chip, and therefore tends to be costly to implement.
Accordingly, there is a need in the art for avoiding the above described limitations associated with conventional reference cell implementations for MRAM.